1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabrication method that may secure a proper dimension margin between contact holes.
2. Description of the Related Art
As the integration degree of semiconductor devices increase with the development of under-30 nm processing technology, the critical dimensions (CD) (e.g., line widths) of patterns for gates, bit lines, vias, contact holes, etc. become smaller and thus, it becomes more difficult to form the appropriate patterns. Particularly, with the increased integration degree, the aspect ratios of patterns also increase, and thus, it is more difficult to perform processes for forming an inter-layer dielectric (ILD) layer.
Here, an insulation layer, such as a Tetraethyl Orthosilicate (TEOS) layer, a High-Density Plasma (HDP) layer, or a Boron Phosphorus Silicate Glass (BPSG) layer, may be used for an inter-layer dielectric layer. However, due to limitations as a gap-fill material, use of TEOS layer or HDP layer as an inter-layer dielectric layer has been difficult.
According to another example, a method of using a Spin-On Dielectric (SOD) layer may be used to obtain excellent gap-fill performance. Here, an SOD layer is formed by applying a polysilazane-based material (e.g., perhydropolysilazane (PSZ)) through a spin coating method and performing a high-temperature thermal treatment. Processes for forming a polysilazane-based SOD layer are relatively simple and have a high throughput.
The polysilazane-based SOD layer, however, is often formed by a thermal treatment performed at approximately 850° C. or higher, where a compositional change and a volume shrinkage may occur due to the fume generated during the thermal treatment and thus cause deformation in pattern shapes. As the inner and lower portions of the polysilazane-based SOD layer are prone to not having complete densification, voids may be produced during subsequent processes.
Because of the above-discussed features of conventional examples, Boron-Phosphorus-Silicate Glass (BPSG) has been often used for forming an inter-layer dielectric layer.
A BPSG layer has an advantage that its gap-fill performance may be increased by increasing the concentrations of boron and phosphorus in the layer and increasing the temperature of a subsequent annealing process.
FIG. 1 is a cross-sectional view illustrating a method for fabricating a semiconductor device according to prior art.
Referring to FIG. 1, an isolation layer 12 to fill trenches is formed by performing a Shallow Trench Isolation (STI) process on a substrate 11. Subsequently, contact plugs 13 are formed over the substrate 11.
Subsequently, an inter-layer dielectric layer 14 is formed over the substrate structure including the contact plugs 13. The inter-layer dielectric layer 14 includes BPSG. The inter-layer dielectric layer 14 is planarized through a Chemical Mechanical Polishing (CMP) process.
Subsequently, contact holes 15 are formed by etching the inter-layer dielectric layer 14, which is cleaned afterward through a cleaning process.
According to an example, BPSG used as the inter-layer dielectric layer 14 may produce byproducts such as boron phosphate (BPO4) crystallite when the concentration of boron and/or phosphorus is relatively high. In such a case, it may be difficult to perform a CMP process. Further, with respect to an etchant used during a dry etch process and a wet etch process, BPSG has a faster etch rate than a silicon oxide (SiO2) layer, where, if the cleaning process is performed rigorously, a bridge 16 may be produced in the resulting structure.
Thus, it may be useful to have a semiconductor device fabrication method that can minimize/reduce the loss of an inter-layer dielectric layer during etching processes by inducing densification locally on exposed BPSG.